The present invention relates to an inverter driving circuit and an inverter control circuit and, more particularly, the invention is preferably applied to a method of adjusting the phase of a drive signal for driving an inverter which converts a direct current into an alternating current.
Motor control methods include a method of driving a motor while converting an alternating-current voltage output from a AC power supply with a converter into a direct current and converting the direct current converted by the converter into an alternating-current voltage with an inverter. For the purpose of power saving, the inverter may be driven using a method in which switching elements constituting the inverter are PWM-controlled.
FIG. 13 is a block diagram showing a schematic configuration of a driving circuit for driving an inverter according to the related art. Referring to FIG. 13, a driving circuit 132 includes an input circuit 52, a noise-malfunction prevention circuit 53, and a driver circuit 55. The input circuit 52 includes a resistor R1 connected between a power supply terminal 91 and an input terminal 92. The noise-malfunction prevention circuit 53 includes a hysteresis comparator 56. One input of the hysteresis comparator 56 is connected to the input terminal 92, and the other input of the hysteresis comparator 56 is connected to a ground terminal 94 through a reference voltage source 57. An output of the hysteresis comparator 56 is connected to the driver circuit 55.
The driver circuit 55 includes a P-channel field effect transistor M1 and an N-channel field effect transistor M2. The source of the P-channel field effect transistor M1 is connected to the power supply terminal 91. The drain of the P-channel field effect transistor M1 is connected to the drain of the N-channel field effect transistor M2 and an output terminal 93. The source of the N-channel field effect transistor M2 is connected to a ground terminal 95, and the gates of the P-channel field effect transistor M1 and the N-channel field effect transistor M2 are connected in common.
The inverter includes switching elements S1 and S4 which are series-connected to each other, and the output terminal 93 is connected to the gate of the switching element S4. For example, IGBTs (Insulated Gate Bipolar Transistors) may be used as the switching elements S1 and S4.
FIG. 14 is a timing chart showing operations of the driving circuit shown in FIG. 13. Referring to FIG. 14, when an input signal 51 is input between the input terminal 92 and the ground terminal 94, the signal is input to the hysteresis comparator 56 through the input terminal 52. Two voltage thresholds or higher and lower voltage thresholds (e.g., 1.36 V and 2.00 V) are set in the noise-malfunction prevention circuit 53 by the reference voltage source 57.
When the input signal 51 is input to the hysteresis comparator 56, the hysteresis comparator 56 compares the input voltage (a′-point voltage) with the lower voltage threshold in the case that the a′-point voltage is in transition from a power supply voltage to a ground voltage and compares the a′-point voltage with the higher voltage threshold in the case that the a′-point voltage is in transition from the ground voltage to the power supply voltage. When the a′-point voltage exceeds the voltage threshold, the output of the hysteresis comparator 56 changes to a high level which results in a b′-point voltage in the form of a rectangular wave. Since the a′-point voltage is compared with the two thresholds or high and low voltage thresholds, it is possible to avoid malfunctions attributable to noises having an amplitude equal to or smaller than the higher voltage threshold minus the lower voltage threshold.
The output from the hysteresis comparator 56 is input to the driver circuit 55, and the b′-point voltage is subjected to current amplification in the driver circuit 55. The signal obtained through the current amplification in the driver circuit 55 is input to the gate of the switching element S4 through the output terminal 93 to charge or discharge a gate capacity of the switching element 4, whereby the switching of the switching element S4 is controlled
Referring now to a gate voltage (c-point voltage) of the switching element 4, the c′-point voltage starts rising with a delay of a delay time Td1 after the b′-point voltage starts rising, and the c′-point voltage starts falling with a delay of a delay time Td2 after the b′-point voltage starts falling. The delay time Td1 is a delay which occurs in the driver circuit 55 itself when the c′-point voltage rises, and the delay time Td2 is a delay which occurs in the driver circuit 55 itself when the c′-point voltage falls.
When the c′-point voltage is applied to the gate of the switching element S4, since the switching element S4 has a parasitic capacity, there is also a delay between a collector-emitter voltage Vce and a collector current Ic of the switching element S4. When the load of the driver circuit 55 is the switching element S4 (P1), a delay time between a point when the c′-point voltage starts rising and a point when the voltage completely rises is longer than that in the case in which the load of the switching element S4 is simply constituted by a capacitor (P2). Let us assume that Td3 represents a delay time between a point when the c′-point voltage starts rising and a point when the collector current Ic reaches 90% of the value that the current assumes when it completely rises.
When the load of the driver circuit 55 is the switching element S4 (P1), a delay time between a point when the c′-point voltage starts falling and a point when the voltage completely falls is greater than that in the case wherein the load of the driver circuit 55 is simply constituted by a capacitor (P2). Let us assume that Td4 represents a delay time between a point when the c′-point voltage starts falling and a point when the collector current Ic reaches 10% of the value that the current assumes when it completely rises. As a result, the circuit as a whole including the driving circuit 132 and the switching element S4 has a rising delay time Ton which is Td1 plus Td3 and a falling delay time Toff which is Td2 plus Td4.
An index Tdead indicating input/output phase characteristics of the entire circuit including the driving circuit 132 and the switching element S4 can be defined as Tdead=Toff−Ton. Depending on the way that the driving circuit 132 and the switching element S4 are combined, there may be a great phase difference between input and output, and the index Tdead may have a great value.
For example, JP-2003-51740 discloses a semiconductor integrated circuit which is added with a terminal to allow a dead time to be set using an external resistor such that the dead time can be kept unchanged even in the case of a signal having a small pulse width. However, when the index Tdead indicating the input/output phase characteristics of the entire circuit including the driving circuit 132 and the switching element S4 has a great value, there is a great difference between the pulse width of the a′-point voltage and the pulse width of the c′-point voltage. Since the controllability of pulse widths is consequently reduced in exercising PWM control, a problem has arisen in that the control performance of the PWM control system is degraded.
In view of the above, it would be desirable to provide an inverter driving circuit and an inverter control circuit capable of adjusting a delay time when a drive signal for driving an inverter rises or falls.